1. Field of the Invention
The present invention relates generally to semiconductor devices and manufacturing methods therefor and, more particularly, semiconductor devices having SOI (Silicon on Insulator) structures and manufacturing methods therefor.
2. Description of the Background Art
With an increase in storage capacity of a memory, a memory transistor used for the storage conventionally becomes miniaturized. This makes it more and more difficult to improve performance of memory transistors. Transistors formed on an SOI layer have much higher performance than that of transistors formed on an ordinary silicon substrate. More specifically, a transistor having an SOI structure has a reduced leakage current, excellent subthreshold characteristics and high current drive capability. Because of these advantages, application of a transistor having the SOI structure is expected to a memory device such as a DRAM or a logic circuit whose element size is smaller than quarter-micron. In the case of a DRAM (Dynamic Random Access Memory), for example, a memory cell formed on an SOI layer can completely eliminate soft error, and because of an extremely small junction capacitance it allows a refresh cycle time to be increased. Thus, a memory cell transistor of a DRAM having the SOI structure achieves much higher performance than that can be achieved by a memory cell transistor formed on an ordinary silicon substrate.
Methods for isolating elements formed on an SOI layer mainly include three types, LOCOS (Local Oxidation of Silicon) isolation, mesa-type isolation and field shield isolation. FIG. 18 is a sectional view showing a semiconductor device having an SOI structure based on conventional LOCOS isolation. FIG. 19 is a view showing a section taken along a direction perpendicular to that shown in FIG. 18. With reference to FIGS. 18 and 19, in the SOI structure employing conventional LOCOS isolation, a silicon oxide film 5 is formed on a silicon substrate 7. An SOI layer 1 is formed on silicon oxide film 5. Active transistors 14a and 14b are formed at a predetermined interval from each other on SOI layer 1. Active transistor 14a is formed of n-type impurity regions 16a, 18a and 16b, 18b consisting source/drain regions, and a gate electrode 13 formed on SOI layer 1 between n-type impurity regions 16a and 16b with a gate oxide film 12 interposed therebetween. Sidewall oxide films 17a and 17b are formed on the opposite side surfaces of gate electrode 13 to be in contact therewith.
Active transistor 14b is formed of n-type impurity regions 16c, 18c and 16d, 18d constituting source/drain regions, and gate electrode 13 formed on SOI layer 1 between n-type impurity regions 16c and 16d with gate oxide film 12 interposed therebetween. Sidewall oxide films 17e and 17f are formed on the opposite side surfaces of gate electrode 13 to be in contact therewith.
In an isolation region located between active transistors 14a and 14b, a LOCOS oxide film 23 is formed for isolating elements. On LOCOS oxide film 23, a gate electrode 13 is formed with a gate oxide film 12 interposed therebetween. Sidewall oxide films 17c and 17d are formed on the opposite sides of gate electrode 13 to be in contact therewith. An interlayer insulating film 19 made of a silicon oxide film is formed to cover the whole surface and contact holes are formed at predetermined regions of the film. In these contact holes, plug electrodes 20a, 20b, 20c, 20d and 20e are buried so as to be electrically in contact with n-type impurity regions 18a, 18b, gate electrode 13 on LOCOS oxide film 23, n-type impurity regions 18c and 18d, respectively. The SOI structure employing LOCOS isolation is realized by the foregoing arrangement.
FIG. 20 is a sectional view showing an SOI structure employing conventional field shield isolation. This SOI structure is identical to that employing LOCOS isolation shown in FIG. 18 with the only difference in isolation regions. In the structure employing field shield isolation, a field shield gate 25 is formed on the isolation region of SOI layer 1. Field shield gate 25 is composed of a field shield gate electrode 23 formed on the isolation region of SOI layer 1 with an oxide film 22 interposed therebetween, and an oxide film 24 formed to cover field shield gate electrode 23. On this field shield gate 25, a gate electrode 13 is formed with a gate oxide film 12 interposed therebetween. The SOI structure employing conventional field shield isolation is realized by the foregoing arrangement.
First, the SOI structure employing conventional LOCOS isolation shown in FIGS. 18 and 19 has a disadvantage that a parasitic MOS transistor is generated at a part of SOI layer 1 whose thickness is reduced due to LOCOS oxide film 23 as illustrated in FIG. 19. The parasitic MOS transistor has a threshold voltage lower than that of an original MOS transistor, so that it can be turned on before the turn-on of the original MOS transistor, causing adverse effects on electrical characteristics of the original MOS transistor. On the other hand, the SOI structure employing conventional LOCOS isolation has a drawback that substrate floating effects (parasitic bipolar effects) cause reduction of breakdown voltages of the source/drain regions of active transistors 14a and 14b. More specifically, holes generated by impact ionization are stored in a channel region of a transistor to increase a substrate potential, while the holes newly induce electrons from the side of the source. As a result, a breakdown voltage between a pair of source and drain regions is reduced. Such substrate floating effect is also a problem in mesa-type isolation.
The above-descried SOI structure employing field shield isolation has a disadvantage that a height of an isolation region is greater than that of other regions to create a large step. This makes it difficult to pattern gates and aluminum interconnections on an isolation region of large height, which results in complication of a manufacturing process.